Daniel Domes, Reinhold Bayerer, Alexander Herbrandt

Infineon Technologies AG

Max-Planck-Straße 5

59581 Warstein, Germany

　　Abstract

　　Increasing efficiency and lowering EMI are important goals for designing power electronic

　　systems. To obtain this, the parasitic inductance of the current commutation loops is under

　　focus. In this paper an overall low inductance module is shown which provides not only low

　　inductance within the half bridge but also low inductance among half bridges itself, e.g. in a 3

　　phase inverter. The new module concept enables not only optimized 3 phase systems but

　　also optimum performance of three level NPC (Neutral Point Clamped) inverters.

　　Introduction

　　In power electronic systems fast transients in voltage and currents are the consequence of

　　the basic functionality. High di/dt values at current commutation in conjunction with parasitic

　　inductance induce voltages across the parasitic inductance L, circuit as shown in Fig. 1:

　　Fig. 1 Simplified half bridge commutation circuit

　　During turn-off of an IGBT, voltage overshoots occur between collector and emitter. Another

　　disadvantage coming along with L is the low resonance frequency of the resonant circuit

　　formed by the parasitic chip capacitance Cchip and the stray inductance L:

　　In Fig. 2 a 1200V/400A low inductance half bridge module is shown having only 5nH internal

　　stray inductance, first presented in [1]. The low inductance value was realized by strictly

　　ensuring strip line design and current flow only in the y-z-plane. The consequences are a

　　dramatically reduced over voltage peak and no ringing (Fig. 3).

　　Fig. 2 Low inductance half bridge module　enabling lowest parasitic inductance by having

　　line-wise DC-connectors enabling the continuation　of busbar strip line even in the module

　　Fig. 3 Turn-off waveforms of the same type of IGBT and diode chips performing once in a standard

　　module (left) and once in the demonstrator module of Fig. 2, both modules are characterized at

　　700V/400A, Tj=25°C (blue: vCE 200V/div, red: iC 100A/div, green: vGE 10V/div)

　　Three phase topology

　　The low inductance half bridge module from [1] seems to be an ideal candidate for realizing a

　　3-phase inverter system. The quite good switching behavior seen in the comparison in Fig. 3

　　is the result of not only optimizing the module but also the bus bar and the capacitor. Such an

　　optimized half bridge system is shown in Fig. 4 left, schematically. As demonstrated in Fig. 4

　　right, the parallel arrangement of three of the half bridge systems leads to a three phase

　　inverter. Often the interconnection between half bridges is not optimized for low parasitic

　　inductance. The target of the work in this paper is to eliminate the inter-half-bridge

　　inductance, as well. This requires an overall strip line design for the whole inverter (3 half

　　bridges) including the DC-capacitor.

　　Fig. 4 Inductance-optimized half bridge system (left) and conventional arrangement of these

　　half bridge systems for obtaining a three phase inverter (right); from one half bridge with DC-

　　capacitor to the others stray inductance still exists

　　Low inductance connection between half bridges is relevant for commutation among half

　　bridges. This happens when the so called zero-state is set by means of the control system of

　　the inverter, for example. Zero-state means that all top and bottom switches are turned on,

　　respectively. Then, a freewheeling loop appears and the impressed load currents are running

　　free through transistors and diodes of either the top or bottom side. No current goes into

　　capacitors anymore and all load branches are connected to the same potential (DC+ or DC-).

　　After this zero state, the modulator continues with non-zero switching states and currents

　　commutate from freewheeling paths into capacitors. The inductance from half bridge to half

　　bridge then reacts with overvoltage causing the above mentioned problems.

　　In Fig. 5 an example for inter-half-bridge commutation is shown in a simplified way. Assuming

　　that the DC-connection to the mains is not applied for the moment of commutation, in the left

　　picture a zero state is shown, whereas all top IGBTs are turned on. Assuming further that the

　　load current in the middle and right half bridge is flowing into the phase connection, the top

　　diodes of the mentioned half bridges are conducting. The sum of these currents is flowing out

　　of the phase terminal of the left half bridge, whereas its upper IGBT is conducting. If the

　　modulator continues with a non-zero state, the upper IGBT of the left half bridge can be

　　turned off, for instance. Fig. 5 right shows the situation directly after the IGBT turn-off. The

　　stray inductors are forcing current flow although the IGBT is already turned off. In this

　　example the consequence is that the energy stored in the stray inductors goes into the DC

　　cap of the left half bridge. This effect is causing an overall higher RMS current of the DC

　　caps compared to low stray inductance design.

　　Fig. 5 Simplified example for inter-half-bridge commutation in a 3-phase inverter with stray

　　inductance in the half bridge to half bridge connection and a pure inductive load; Left: inverter

　　in zero state (all upper IGBT gates are turned on, therefore marked as bold), current coming 　　      from middle and right half bridges is going through upper IGBT in the left half bridge; Right:   

      upper IGBT of left half bridge is turned off because modulator continues with non-zero-state,

　　energy stored in parasitic load inductors is going into left DC-link capacitor

　　Three-level-approaches

　　Three level NPC inverters are usually built out of standard modules. According to Fig. 6 this

　　means using half bridge packages with three different electrical setups.

　　Fig. 6 Three level NPC1 inverter leg built out of standard modules (green FF, blue FD, red DF)

　　Depending on the combination of the sign of output voltage and current different

　　commutation loops exist where two (short commutation) and even three (long commutation)

　　half bridge modules are involved [2]. Therefore the low inductive connection from half bridge

　　to half bridge is quite of interest, especially in 3 level application.

　　Proposed Solution

　　Low inductance commutation loops between half bridge systems can be arranged by strictly

　　following the principles mentioned in [1]. These are

　　 Consequent realization of strip line conductors without interruptions in geometry

　　 Arranging the commutation current flow always in y-z-plane (see example in Fig. 2)

　　The outcome of that is a module concept as shown in Fig. 6. This approach combines three

　　half bridges, within which the chips are paralleled along the x-axis. Three have bridges are

　　arranged behind each other along the y-axis. To achieve lowest inductance throughout the

　　whole arrangement of 3 half bridges a multilayer DCB is used. It allows to run a DC- layer

　　over the whole length of the module, along the y-axis. The individual half bridges are carried

　　by a second layer of DCB, which connects down to the first layer at each DC- side. DC+ and

　　Phase (Ph1 to Ph3) is brought up by means of a line wise connector for each individual half

　　bridge. Strip lines in the multilayer DCB and above the chip layer result in an overall low

　　inductance inverter.

　　Fig. 7 Three-phase concept module for lowest overall inductance

　　Conclusion

　　For three phase systems and three level NPC circuits the low inductive connection of

　　individual half bridge circuits is an important task. A new module concept is demonstrated

　　which combines properties, lowering the inductance while fulfilling the need of current flowing

　　in the y-z-plane of Fig. 7. Following on this design lead to an overall reduced inductance,

　　excellent current sharing and lowered RMS current at the DC capacitors.

　　References

　　[1] Reinhold Bayerer, Daniel Domes: Power Circuit design for clean switching. CIPS 2010,

　　Nuremberg, Germany.

　　[2] Zhang Xi, Uwe Jansen, Holger Rüthing: IGBT power modules utilizing new 650V IGBT3

　　and Emitter Controlled Diode3 chips for three level converter. PCIM Nuremberg 2009,

　　Germany.